Circuit simulation and timing analysis software, hereinafter timing software, is commonly used during design of integrated circuits to determine whether circuitry meets timing requirements. Common timing software includes analog circuit simulators such as Spice, static timing analysis software like HiTas, and programs like Pathmill and Timemill, as well as other programs. Timing software includes dynamic timing software, which models circuit performance, and static timing software, which compares total path delays against limits. Timing software generally works by analyzing or simulating a computer model of circuitry of an integrated circuit, hereinafter the circuit model.
It is known that timing software produces results that are highly dependent upon the accuracy of the circuit model. It is also known that the execution time and memory requirements of timing software is highly dependent upon the complexity of the circuit model, with complex circuit models requiring much greater execution time for analysis than simple circuit models.
Every real integrated circuit has parasitic resistances and capacitances. These are resistances and capacitances that exist in the circuit not because they are desired circuit elements, but because on-chip wiring and diffused regions have resistance and capacitance. It is well known in the art that timing software requires circuit models incorporating the effect of parasitic resistance and capacitance if accurate results are to be produced. In particular, it is known that parasitic resistance and capacitance of on-chip wiring, or interconnect, is particularly significant in modem, high speed, submicron, integrated circuits. The term interconnect as used herein includes all on-chip signal wiring, including diffused regions and polysilicon, whether silicided or not, and metal lines.
Circuit extraction software, available from vendors including Cadence and Mentor Graphics, is commonly run on integrated circuit designs to extract parasitic resistances and capacitances. Software for extraction includes Diva, Dracula, Hyperextract, xCalibre, and other programs. These resistances and capacitances are then incorporated into circuit models for use with timing software. It is known that these circuit models can become extremely complex during analysis of designs for high performance submicron integrated circuits.
It is desirable to simplify complex circuit models, such as may be produced by circuit extraction software, so that timing software will run in reasonable time and memory. It is particularly desirable to simplify circuit models for dynamic timing, since dynamic timing run times are often exponential with respect to model complexity.
It is known that some extracted resistances and capacitances have much greater impact on timing software results than others.
A typical extracted circuit model includes models of many active elements. Typical active elements may include CMOS transistors as P and N channel transistors, each of which has gate capacitance. Circuit models may also include other types of transistor-level active elements, such as bipolar transistors, silicon-germanium bipolar transistors, as well as gallium arsenide bipolar and MESFET devices. An extracted circuit model may also include active elements such as higher-level logic elements, or logic gates. These higher level models may also include modeled input capacitance. Circuit models also may include many resistors for modeling interconnect resistance, and many capacitors for modeling interconnect capacitance.
A prior technique for simplification of complex circuit models is to remove all resistances from the model that have values below a preset minimum resistance threshold. Similarly, all capacitances below a preset minimum capacitance threshold may also be deleted. Most extraction software is capable of ignoring resistance and capacitance below threshold values. While this is simple to implement and can greatly simplify a circuit model, the simplification may introduce significant error into timing software results.
Some of this error results because the impact of a particular resistance or capacitance depends on other model elements and circuit topology. For example, even a small capacitance can cause significant timing delay if it is driven through lengthy interconnect having large resistance. If the small capacitance is deleted from the model, that delay will be ignored.
Several techniques for simplification of circuit models have been published. Such methods are reported by A. J. van Genderen, et al, Extracting Simple but Accurate RC Models for VLSI Interconnect, IEEE International Symposium on Circuits and Systems, 1988; A. Devgan et. al. Realizable Reduction for RC Interconnect Circuits, IEEE/ACM International Conference on CAD, November 1999; B. Sheehan, TICER: Realizable Reduction of Extracted RC Circuits, 1999 IEEE/ACM International Conference on CAD, November 1999; and S Su, et. al, A Simple and Accurate Node Reduction Technique for Interconnect Modeling in Circuit Extraction, IEEE International Conference on CAD, November 1986.
Sheehan, incorporated herein by reference, computes nodal time constants for nodes of the circuit, classifying these time constants into slow, normal, and quick classifications. Nodes having time constants substantially faster than the frequency range of interest are classified as quick nodes; while those having time constants substantially slower than the frequency range of interest are classified as slow nodes. Quick and slow nodes are then eliminated from the circuit.
In particular Sheehan finds instances of quick nodes internal to, and coupled to, normal nodes in an RC network. Sheehan then removes the internal quick node of each instance by effectively transferring nodal capacitance, conductance, and other circuit elements from the quick node to the normal node. Sheehan thereby constructs a simplified network having normal simulation elements such as resistors and capacitors.
Most existing RC network simplification methods focus on reduction at internal nodes of a RC network. These algorithms typically avoid alteration or simplification at terminal nodes of the RC network, such as those attached to device inputs.
It is known that simulation models of CMOS and other field-effect transistors include models of significant input capacitance. This capacitance is nonlinear with voltage and represents a combination of parasitic capacitances and gate capacitance. Each transistor may have a gate resistance associated with it.
A circuit model includes a network of resistors, capacitors, and active elements. The circuit model may incorporate parasitic resistances and capacitances as extracted from an integrated circuit layout. Typically, each input of an active element of the circuit model is associated with a branch resistance; branch resistances may include a portion of resistance of a gate of each MOS transistor. Each active element is associated with an input capacitance.
Each input to each active element is inspected. In a CMOS, BICMOS, or SIGE integrated circuit, these inputs to active elements include gate connections of N and P type MOS transistors. They may also include base connections of bipolar and heterojunction transistors. Should the circuit model at that point be a capacitance (including an input capacitance of the active element and may include parasitic capacitance), driven through a branch resistance, a time constant for the capacitance and branch resistance is calculated.
If the time constant of the branch resistance and the capacitance is less than a predetermined threshold, the resistance is removed from the circuit without altering other resistances of the circuit model.